CSCI E-92: Application Note 26

Enabling UsageFault, BusFault & MemManage Faults
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As shown in the ARMv7-M Architecture Reference Manual, Issue E.b,
20141202 DDI0403E_B_armv7m_arm in Table B3-4 Summary of SCB registers
(continued) on page B3-653, register SHCSR is reset to 0x00000000.  As
shown in the same manual in section B3.2.13 for the System Handler
Control and State Register, SHCSR on pages B3-663 through B3-665, this
means that UsageFault (bit 18), BusFault (bit 17), and MemManage Fault
(bit 16) are all disabled.

We want to have UsageFault, BusFault, and MemManage Fault all be enabled
during execution of your operating system.  This can be accomplished with
the following C statement:

SCB_SHCSR |= (SCB_SHCSR_USGFAULTENA_MASK |
              SCB_SHCSR_BUSFAULTENA_MASK |
	      SCB_SHCSR_MEMFAULTENA_MASK);

As noted in the same manual in section A3.2 Alignment support on page
A3-65 through A3-66, some unaligned accesses always generate an
alignment fault, while others need to be enabled.  Therefore, to
enforce all faults on unaligned accesses, we need to enable other
specific faults by setting the SCB_CCR_UNALIGN_TRP_MASK bit in the CCR
register.

SCB_CCR |= SCB_CCR_UNALIGN_TRP_MASK;

Details on the Configuration and Control Register, CCR are given in
section B3.2.8 on page B3-660.

If either signed or unsigned integer divide instructions (SDIV and
UDIV) are executed with a divisor of 0, then, by default, those
operations will return 0.  This is detailed in the same manual in
section A4.4.6 Divide instructions on page A4-110.  In order to enable
a divide-by-zero UsageFault exception if division by 0 is attempted,
the DIV_0_TRP must be enabled as follows:

SCB_CCR |= SCB_CCR_DIV_0_TRP_MASK;

Stack frame alignment can be enforced by setting the
SCB_CCR_STKALIGN_MASK bit in the CCR.  See B1.5.7 Stack alignment on
exception entry on page B1-591 in the same manual.

SCB_CCR |= SCB_CCR_STKALIGN_MASK;

Of course, all of these configurable traps can be activated in one statement as follows:

SCB_CCR |= (SCB_CCR_UNALIGN_TRP_MASK |
	    SCB_CCR_DIV_0_TRP_MASK |
	    SCB_CCR_STKALIGN_MASK);